KiCad Joulescope front panel baseline design now available

The connector is a Molex part and it has a locking tab that also is polarized.

171856-0102

In the photo the mating connector is not the proper mate, it was just what I had on the PSU cable. Molex 22-01-2027 has a “friction ramp” that locks it in place.

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Why are the connector pads on the JS220 footprint set to “None” for “Pad connection”? The net effect is that pours/fills on the bottom layer where the connector pads are, wont connect to the pads. You’d have to draw tracks to the pads.

I recall there was a suggestion for the JS110 footprint to remove thermal reliefs for the high current pins at least, to allow a solid connection. It seems the JS220 pads are the polar opposite!

Learning KiCAD is still on my todo list. @simonmerrett was kind enough to create the KiCAD JS220 front panel template. Perhaps he has a quick answer?

Yes, you do want to use sufficient copper on the front panel for the current terminals. For USB @ 500 mA, this is less of an issue. If you are using PD @ up to 5 A, then you definitely need to pay attention and provide sufficient copper.

Are we talking about JS220 or JS110? I think only JS110 panels are in the repo.

@hraftery I’ve just opened the baseline board in KiCAD V6.0, which is the oldest version I run atm. It appears the project was generated in V5.x by the banner at the top. In V6.0 you can see that the pads have a solid connection to copper zones.


So my presumption is that V7 or V8 has done a best-effort conversion and has not maintained the intent of the V5.x design. This is supported by the warning I get when I open them in V8.0:

Sorry this isn’t the desired result but hopefully explains how you’ve ended up with something we didn’t intend.

Based on this other topic, I think that this is for a JS220. Here is the KiCAD JS220 baseline repo:

GitHub says the KiCAD baseline was contributed by MATTERealise, which I think is you, @simonmerrett ! Thanks for the JS220 front panel contribution, too!

Ah, that makes more sense, although I just assumed the link at the top was relevant to ongoing discussion.

So having created JS220 panels in KiCAD V6.0 (I think - opens fine in V6.0 with no warnings) it does seem that these pads are as described - no connection by default to copper zones. The parent footprint has the setting to inherit connection to copper zones depending on what the zone is set to. For the individual pads, we have the options:

  • Inherit from parent footprint (which in turn will inherit from the zone, under current settings)
  • Solid
  • Thermal relief
  • None (although I’m guessing we don’t want that?)

All these settings take seconds to set but I realise that you may want a different default.

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I suppose the two sensible options are:

  1. Inherit from parent footprint.
    • with a note somewhere that the designer should ensure any thermal reliefs they apply to the pads are suitable for the current spec they’re targeting.
  2. Solid
    • then it’s the same as FP110 (should it be?), and the designer is relieved of the effort.

Based on that the second option seems like the right thing to do, to provide a gold standard template.

I’m just concerned that if the designer decides to flood fill the whole bottom side with GND, then they have a big thermal sink on a single pin of that connector (may be a pain to solder), with no improvement in current carrying (because the high current pins aren’t connected by a flood fill). Setting the pads to Solid sort of assumes a certain layout, where the high current pins have individual flood fills.

So I’m leaning slightly to the second option. First option is good for consistency, but second option plus a note to say “pins x and y are high current - ensure low impedance connection” might have slightly higher success rate.

In the case where there is a low current front plate design, I think it would be unlikely the designer would select a high current I+ or I- net for any copper zone they decide to put on the bottom (facing inside the enclosure) layer. In that scenario, surely they would be more likely to set chassis ground as the copper zone net, as advised for the top layer in the baseline drawing and suggested by you. But what if they consider I- or I+ should be the same as GND? I’m not sure except I- in the case of low-side measurement. Seems like one of the less frequent front plate designs but I suppose it is there as an option.

Regarding the scenario where we have high current, we could assign copper zone connection properties individually per pin. For example, Solid copper pour connections to I+ and I- pins, and assign either From parent footprint or Thermal relief for V+ and V-.

Good point. Lots of ways this template/baseline could be used.

Yeah, it doesn’t solve the potential manufacturability issue, but it does communicate something useful - that as the designer you should think twice about using thermal reliefs on these particular pads. It’s not perfect, but it does carry a bit of design intent through.